In a typical CMOS image sensor readout circuit, there is only one pair of sample-and-hold circuits for storing the sampled reset and pixel signal values output by a selected row. These two sample-and-hold circuits are read out sequentially, with either the pixel signal level (“PIX”) read out first, followed by the reset level (“RST”), for example as is typical in a 3-T pixel readout scheme, or RST read out first, followed by PIX, for example as is typical in a 4-T pixel readout scheme. Readout is performed column-by-column.
To increase the readout speed for high resolution image sensors, the ping-pong readout architecture can be adopted. The ping-pong readout architecture has two pairs of sample-and-hold circuits per column, for example as depicted in FIG. 1. In alternating phases, each pair of sample and hold capacitors will act as the “sampling pair” while the other, opposing pair acts as the “output pair,” as follows. For example, referring to FIG. 1, in a first phase, the PIX and RST signals for a given row, row n, are sequentially output from the pixel to a pixel output line (101). By operation of switches (104 and 105), these signals are sampled and held on a first pair of capacitors (102 and 103), during which such phase this first pair acts as the sampling pair. After this first phase, in a second phase, the first sample and hold capacitor pair (102 and 103) becomes the output pair and, by the action of switches (106 and 107) the sampled PIX and RST signals are output to respective PIX and RST signal bus lines (114 and 115). During this second phase, the second pair of sample and hold capacitors (108 and 109) acts as the sampling pair and receives, by the action of switches (110 and 111), and stores PIX and RST signals sequentially output from row n+1 to the pixel output line (101). This operation is followed by a third phase, wherein the first pair of sample and hold capacitors (102 and 103) again becomes the sampling pair, receiving PIX and RST signals from row n+2 while the second pair acts as the output pair, by the action of switches (112 and 113), outputting stored signals from row n+1 to the RST and PIX signal bus lines (114 and 115). The RST and PIX signal bus lines may input to a signal processing or storage element, for example an ADC, data buffer, or memory element.
Because there are two pairs of sample-and-hold capacitors, the ping-pong architecture allows the simultaneous readout of one row during the sample- and hold phase of the next row. The overlapping timing of these operations decreases the time necessary for reading out each row and increases the frame rate. Accordingly, this ping-pong architecture advantageously allows high speed operations, for example in global shutter or extremely high frame rate cameras.
The use of a ping-pong architecture has certain shortcomings and complications. First, adding the second pair of sample-and-hold circuits will increase the height of the circuit as well as adding extra control signals for selecting between the two sample- and hold pairs. Second, if the column readout pitch stays the same as pixel pitch, twice as many column readout select signals need to be placed into a single column, which results in increased parasitic capacitance among components. For example, a crowded column output architecture results in increased parasitic capacitance between the pixel output line and the sample-and-hold capacitor top plates, and between the sample-and-hold top plates and the readout output line. A third issue in ping-pong architecture is that the readout timing scheme becomes more complicated because of the overlap between previous row's readout and the next row's sample-and-hold phases. Big crosstalk spikes or missing codes may be produced in the neighboring readout circuit due to the parasitic capacitances caused by nearby operations.
Presented herein is a modified ping-pong architecture which addresses the shortcomings of typical designs. Described herein are novel layouts for ping-pong architecture, which isolate sensitive components from sources of capacitance or other interference. Also disclosed are improved timing regimes that help prevent the problematic crosstalk and parasitic capacitance issues inherent in ping-pong architecture.